IC Design Services Verilog-A Best Practices
Below Best Practices We Use for Verilog-A Models;
General Concepts
Always remember that the model code will execute every simulator iteration. Avoid recursion and analog signal feedback. Group the code functions so that someone translating into physical components can understand the signal flow. Simple straight line code with excessive comments results in the best model, physical correlation. Avoid manipulation of the pin voltage, currents in you code(Pin functions interact with the simulator matrix) and never change the context of your pin forcing functions.
- Avoid "exp" function Unless your really need It.
- Avoid Feedback Loops in the Code that require simulation Matrix Convergence
- Understand the Nature of your pin signals before using "slew" and "transition" Statements
These Functions can slow your code execution if used on the wrong type of signal
- Use the Asserted Form of the Integrator function to Avoid Numeric overruns
- Use the "cross" function rather that "If" whenever possible.
- Use the "$strobe" function to insert simulation de-bug information into the standard output stream
- Be sure that all analysis types have an initial condition
Follow this link to see a very simple example of the Verilog-A code construction.
Let us show you how the create compact Verilog-A models that simulate efficiently and add value to your engineering projects.
Copyright 2009 IC DESIGN SERVICES