// File=VcmPwr.va // VerilogA Level 0 Model For HDD Voice Coil Power Amplifier // Pins; // 1. VDD - Bias Power // 2. VHSD - High Side Gate Drive Bias // 3. VM - Primary Input Power // 4. VSS - Return // 5. VCMP - Positive Power Output // 6. VCMN - Negative Power Output // 7. VREF - Error Voltage Common Mode Voltage // 8. VERR - Voltage Control Input // 9. Mode - Linear/Switcher Control Voltage // ----------- Define Behavior ------------------------------- // if Mode=0 Output Slew Rate is Linear // if Mode=1 Output Slew Rate is Fast // VcmP = (VM/2) - [Av*(VERR - VREF)] // VcmN = (VM/2) + [Av*(VERR - VREF)] `include "constants.vams" `include "disciplines.vams" module VcmPwrAmp(VDD,VHSD,VM,VSS,VCMP,VCMN,VREF,VERR,Mode); inout VSS,VHSD,VM,VSS; output VCMP,VCMN; input VERR,VREF,Mode; electrical VDD,VHSD,VM,VSS,VCMP,VCMN,VERR,VREF,Mode; // Parameters parameter Av=4 from (1:10); parameter SlewLin=1.0e6 from (0:inf); // LinMode Output Slewrate parameter SlewSwx=1.0e7 from (0:inf); // SwxMode Output Slewrate // Variables real VcmpMag,VcmnMag,OutSlew; integer i,j,k; // Generic Integers real x,y,z; // Generic Real analog begin @(initial_step) // Initialize begin $strobe("Vcm Power Level 1 Model"); end @(final_step) begin $strobe(" Vcm Power Level 1 Model End "); end // Linear OR Switching Mode if ( V(Mode) > 0.5*V(VM) ) OutSlew=SlewSwx; else OutSlew=SlewLin; // Output Calculators and Limiters VcmpMag=(V(VM,VSS)/2.0) - (Av*V(VERR,VREF)); VcmnMag=(V(VM,VSS)/2.0) + (Av*V(VERR,VREF)); if ( VcmpMag > V(VM) ) VcmpMag=V(VM); if ( VcmpMag < V(VSS) ) VcmpMag=V(VSS); if ( VcmnMag > V(VM) ) VcmnMag=V(VM); if ( VcmnMag < V(VSS) ) VcmnMag=V(VSS); // Output Vector V(VCMP,VSS) <+ slew(VcmpMag,OutSlew,-OutSlew); V(VCMN,VSS) <+ slew(VcmnMag,OutSlew,-OutSlew); end endmodule