A switched capacitor power on delay, reset circuit(POR) for a switching regulator based power management system.
The circuit design implemented a power on reset delay in the milli-second range using switched capacitor design techniques. The block physical circuit design schematics were completed and added to the switching regulator modules for top level system simulation. Simulation cycle time reached 6 days on a very fast simulation server farm. The top level simulations were on critical path for project release to the mask shop. A Verilog-A model was written and de-bugged for the POR block. The model was added to the Cadence view list for the physical block and compared to the physical schematic performance. When the performance was judged equivalent(note there were no simulation convergence issues at this level of complexity) the top level view switch list was modified to use the Verilog-A model rather than the physical block and the top level simulations re-started. The simulation ran much faster, but crashed due to non-convergence. A root cause analysis showed that the problem was caused by use of an "ideal switch" discussed in the Verilog-A specification…. See code fragment below
If (closed) v(p,n) <+ 0 ; Switch Resistance is Zero
else i(p,n) <+0 ; Switch Resistance is Infinite
The switch caused a convergence issue due to time step control in the simulation solution matrix. Examination of the physical vs Verilog-A model simulation slowed that the time step was shrinking to the point of non-convergence, but the matrix complexity was low enough to find a solution. As the simulation complexity increased the convergence diminished until failure occurred. The switch was eliminated and convergence problems disappeared. The top level simulations were completed with an average simulation cycle time reduce by 10X and the design database was released on-time. The lesson learned was good code design is just like good analog circuit design. Use experience to create a set of Best Practices.