The first principle of analog IC design is the concept of matched pairs. That is, two circuits elements placed in close proximity have equivalent characteristics. Statistical design recognizes that proximity device parameters are matched, but not exactly equal. Semiconductor manufacturing produce devices with "batch" and "mis-match" variations. Batch variations represent the average device on a die, on a wafer, in a lot, in a large volume of manufactured wafers. Mis-match variations are caused by geometric and process effects on devices in proximity.

Batch variations are typically specified in the PCD(Process Control Document) as minimum/maximum end points. Typically device parameters; VTH, KP, and TOX are specified. Our experience at IC Design Services suggests that most CMOS process PCD specifications represent between 6 and 9 standard deviations of the process capability. 6 sigma(2CPK) design produces analog parametric yield loss that is small compared to the defect limited yield for a given die size.The practical effect of 9 sigma design is analog blocks that are more costly than required for a given application. Cost effective analog design requires commitment from the front end to characterize and supply accurate process capability data.

According to Pelgrom et al (see reference) the matching(1 Sigma) of two MOS devices in close proximity to each other can be described by a threshold and transconductance matching factor. Both factors track the total gate area according to;

Threshold mis-match(dVth) => vtMatch/SQRT[w*l] ; vtMatch => Process Threshold Matching Factor(Tracks line width)

Transconductance mis-match(dKp) => kpMatch/SQRT[w*l] ; kpMatch => Process Transconductance Matching Factor

In standard CMOS processing the matching factors vs technology node tracks technology feature size and can be approximated by equations below;

vtMatch(mv) = 22*(1 - .9*(1u - xFeaure)) ; xFeature(microns) - Technology Feature Size in Microns.

gmMatch = 0.02*( 1 - 0.9*(1u - xFeature))

.... Many analog centric wafer foundries supply matching data. Check to see if your foundry offers a "Analog Matching Report".

Consider the first order expression for MOSFET drain current(Saturation);

ids = (w/2l)***KP***(vgs - **VTH**)^2 ; Bulk tied to source

KP = μ*εox/tox **VTH**= VFB + Φs + {(tox/εox)*SQRT[2q*Nch*Φs]*SQRT[Φs]} Φs=(2kT/q)*ln[Nch/ni]

μ= Channel Mobility , VFB= Flat Band Voltage, tox=Oxide Thickness, Nch=Bulk Concentration

From the statistical design perspective KP and VTH have a common set of wafer process parameters and are statistically correlated. A physics based statistical modeling system would modulate process parameters(tox,Nch,....) and not the the resulting parameters(VTH,KP). At IC Design Services, we have experience with Physics based statistical design systems. Please contact us if you would like to develop this capability. Given the situation where corner based models are available, mis-match effects can be evaluated using the modified equation;

ids = (w/2l)***KP*(1 + dKP)***(vgs - **VTH- dVTH**)^2 ; dKp= kpMatch/SQRT[w*l] , dVTH= vtMatch/SQRT[w*l]

REFERENCE

M. J. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers. "Matching properties of MOS transistors". IEEE J.

SolidState Circuits, vol. 24, no. 5, pp. 1433--1439, Oct. 1989