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Statistical IC Design ; Analysis
Statistical analysis of analog IC design data is typically performed using either RMS or Monte Carlo techniques.

RMS analog Design analysis is straight forward in that the designer defines elements where matching is significant to meeting a particular specification, then modulates the mis-match of each elements 1 standard deviation. The output of each RMS run is subtracted from the nominal run and stored. N matching elements requires N+1 simulator runs where run 0 is the no mismatch case. The error of the parameter under test is;

    dVx(1 Sigma) = SQRT{ SUM[v(i) - v0][i=1,n] ] ; v(i) is the measured output from each mis-match run.

The experiment is configured so that two pieces of information are available; the RMS error and the error associated with each mis-match component. Feedback on elements mis-match vs specification error assist the circuit designer in trading off Silicon area against performance.

Monte Carlos analysis does not require the designer to pre-define which elements contribute to error. Each element has Gaussian mis-match applied according to the model definitions. The output data is used to calculate specification statistical error. The issue with this approach is whether the EDA software platform back annotates the mis-matches so that the design can determine which elements are problematic. However, a specification compliance matrix can be extracted

    Statistical Models Support Both RMS and Monte Carlo with Simple Configuration Variables
    RMS evaluation for Analog Blocks... Design --> Evaluation --> Design Optimize Cycle
    Monte Carlo for Final Design Verification and Spec Compliance Matrix.

A SCM is a table based method for evaluating the yield impact of a given specification. For example, the table below shows a SCM entry for a bandgap circuit.

| ---------------- Specification -----------------------   | ------------- Simulation ---
      Parameter             Symbol    Min      Typ     Max   Mean    Sd     MeanError  specSd
System Voltage Reference |  Vbg   | 1.225 | 1.250 | 1.575 | 1.252 | 0.01  |  .16%    | 2.5

The projected yield loss for this parameter is 8.2%. The level of yield loss is above the typical defect limited yield and would result in either re-design or the addition of trim.