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Statistical Integrated Circuit Design is a design verification methodology where specified device specifications are simulated and evaluated statistically. Traditionally, wafer foundries supply "corner simulation models" that represent shippable process end points. In many cases these corners represent 9 standard deviations of the process capability. Further, most wafer foundries do not supply models that comprehend device mis-match.

The modern mixed signal IC could contain millions of active devices operating in either the analog or digital domain. The IC specification could exceed 100 printed pages and 1000 specified line items. Time to market constraints combined with the desired to reach defect limited yield in less than six months has placed the analog IC Circuit designer in a paradox; over design or increase risk to achieve design to cost. Statistical design allows the designer to mitigate risk and achieve the desired overall project yield.

Statistical IC design techniques enable Design to Cost and Time to Market by evaluating circuit designs over both batch(wafer process batch variations) and mis-match(device to device variation on the same wafer). At IC Design Services, we have seen the benefits of statistical design(see our project example pages) over many projects. For our semiconductor customers that have not adopted statistical methodologies or using wafer foundries that do not offer statistical modeling support we offer the following services;

  •   Conversion of Corner Spice Simulation Models to Statistical
  •   Addition of Mis-Match Modeling Capability to Corner Models
  •   Process PDK Modification to Support Mis-Match Models
  •   Statistical Simulation Data Extraction and Analysis Tools

We have experience building statistical modeling systems for Spectre(Cadence Framework), Hspice, Smartspice with or without  Monte Carlo Analysis. Any Spice simulator can be used to evaluate statistical performance. Contact us for more information or a quotation


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Statistical IC Design